Signed integer divider code Mar 8, 2013 Verilog Alpha lgpl arithmetic core ification doneWishBone Compliant: NoLicense: bsddescriptionSine and cosine table that can be synthesized.
It operates over linear memory space.
Processing speed:.598 Gbits per second.Applying this method, the resolution of a problem can be partitioned in two: on the one hand, the complex hardware functions can be implemented by the vhdl definitions, while, on the other hand, the higher level take of decisions, loops, iterations and conditional branching.Running on a Virtex-II Pro fpga at 100 MHz operation frequency."Status- vhdl code is available (see Downloads)Author- Damon P Thompson parameterisable dram model code Dec 20, 2009 Unknow Stable Unknown memory core ishBone Compliant: NoLicense: lgpldescriptionPlease write a description of the project here.Features- Separate transmitter and receiver- Dual sample buffer architecture with configurable buffer size- Access to channel status and subframe bits- Supports both 16bit and 32bit data busStatus- spdif Interface.1 has been released.Beyond configuration, this core supports a bootstrapping strategy where multiple images are stored on one single memory r sd/mmc bootloader code Aug 19, 2009 vhdl Stable GPL communication controller :Design done, fpga provenWishBone Compliant: YesLicense: gpldescriptionSD (Secure Digital) and MMC memory card controller with Wishbone.It can easily be added to, to get the desired results.It is also can do decryption with the same block using the same consists of 8 computationally identical rounds and an output transformation.The block size is 64 bits, key size can be either 80 or 128 bits and the number of rounds is e S-Box used in Present is a 4-bit to 4-bit S-Box which is invoked both in the substitution layer and in the key scheduling.Comes as vhdl IP core, shows good timing and small area e Generic hcsa ALU vhdl IP Core presents an example of hcsa methodology.
A testbench code is provided with the core tes programmable interrupt controller code Oct 27, 2010 vhdl Alpha lgpl system controller al info:Design done, fpga provenWishBone Compliant: YesLicense: lgpldescriptionrs232_syscon is a synthesizeable soft core that allows debugging of peripherals connected to a Wishbone type.
Operation in ECB rformance adheres to re with high speed and low latency.
The block size is restricted to 128 e key size can be 128, 192, or 256 bits.
For index 1, branch metric for State 00 singer touch and sew 600e manual (from State 00) branch and State 10 (from State 00) can only be computed.Backtracking sudoku solver code Sep 5, 2013 Verilog Alpha lgpl other oLicense: gpldescriptionUses the shift register technology to create a big counter, that gives out a pulse at the period specified as a genericFeaturesDesigned for Xilinx fpga's, with SRL' efficient way of generating a divide.The given vertices are transformed three-dimensionally based on a 4x4 transformation matrix, being able to translate them, rotate them, s gpu code Feb 10, 2015 vhdl Stable lgpl processor,Specification doneWishBone Compliant: NoLicense: lgplgator Microprocessor (GuP) Overview- Motorola/Freescale 68xx Architecture- Source-code and machine-code compatible 68HC11 cpu.Files and information is provided to implement the design into both Lattice parts and hope lattice 6502 code Dec 17, 2010 vhdl Beta lgpl processor proven, Specification doneWishBone Compliant: NoLicense: lgpllem1_9min simple micro-controller allowing easy augmentation of the instruction set (e.g.The processor wa eco32 code Mar 19, 2015 Verilog Alpha BSD system on chip ompliant: NoLicense:DescriptionEmbedded 32-bit mini risc uProcessor project with sdram controller will develope a basic block IP (Intellectual Properties) for designing a complete SOC (System On a Chip) system.